In a conventional flash EEPROM ("flash" indicating all memory cells or sectors of cells can be erased at once), memory cells are simultaneously erased to a low threshold voltage and then programmed, either individually or in small groups, to a high threshold voltage.
Another conventional EEPROM erase voltage application is illustrated in the memory cell 10 of FIG. 1 (prior art) and the programming voltages for this cell are illustrated in FIG. 2.
In this conventional stacked gate flash memory, all the memory cells must be programmed before the erase pulse application to avoid over-erasure problems. This takes about 2.6 seconds in a 16 Mb memory even if 8-byte page mode programming and a 10.mu. second pulse are utilized. In contrast, the "erase" pulse application and the "verify" cycle each take about 500 ms. Thus, the erase period length is dominated by the programming-before-erase cycle.
In the conventional erasing scheme shown in FIG. 1, the high voltage (12 V.) is applied to the source diffusion layer 12 and the control gate 14 is grounded. Electrons 16 tunnel from the floating gate to the source by means of F-N tunnelling mechanism. In addition, electron-hole pairs are generated in the substrate by the band-to--band tunnelling. The holes are accelerated by the large lateral electric field between the source and substrate leading to avalanche multiplication. Some of the resulting hot carriers are injected into the tunnel oxide and, unfortunately, degrade the endurance characteristics of the memory cell. Moreover, as the scaling of the memory cell decreases the breakdown voltage of the source junction, a high erase voltage cannot be applied to the source.
As illustrated in FIG. 2, programming of the conventional cell 10 is activated by grounding the source 12, applying the high voltage to the control gate 14, which causes channel hot-electron (CHE) injection into the floating gate 18.
In this scheme, as each memory cell is programmed with channel hot-electron injection, the maximum number of memory cells programmed simultaneously is limited because of the large programming current needed. To overcome the above drawbacks, i.e., programming time before erase, and lowered endurance characteristics after multiple program and erase cycles, a Mitsubishi flash EEPROM memory cell 22 is illustrated in "flash erase" mode in FIG. 3 and "flash program" mode of FIG. 4. This devise utilizes the F-N tunnelling concept to program each cell simultaneously. In this erase application of FIG. 3, a +5 voltage is applied to source 24 and a -12 voltage is applied to control gate 26.
FIG. 4 illustrates the programming voltages on a cell that utilizes a back gate bias scheme by applying a generated negative 2 volt bias to substrate 28. In this case +12 volts is applied to control gate 26. This scheme induces an electric field across the gate oxide 30 large enough to activate F-N tunnelling to charge floating gate 32. Since all memory cells can be flash programmed simultaneously, the programming-before-erasure time period and subsequent erase operation time is significantly reduced, and the endurance over hundreds of erase/write cycles is enhanced.
U.S. Pat. No. 5,126,808 issued to Montalvo et al. on Jun. 30, 1992 discloses a flash EEPROM array architecture including a plurality of pages. Each page of the array is isolated from other pages in the array during reading, programming, and erasing of the page. The architecture of this invention includes means for erasing through the gate of the flash EEPROM cell. The erasing voltages and programming voltages are indicated on FIGS. 5 and 6, respectively. Erase is accomplished by a -12 volt control gate 34 signal and a ground or zero volts source 36 voltage for several hundred milliseconds. Programming is done by applying a +12 volt gate signal for 10.mu. seconds, with zero volts on source 36 and +6 volts on drain 38 charging floating gate 40 by channel-hot electron injection.
A brief discussion of disadvantages of FIGS. 3-6 is as follows:
Flash erase to a low V.sub.t, as in FIG. 3, is susceptible to a broad distribution of erased V.sub.t and possible over-erase. The maximum erased V.sub.t allowed must be sufficiently high so that the lowest erased V.sub.t is still well above 0 V. A high allowed erase V.sub.t implies that the cell current during read operation will be low and additional time will be required for reliably sensing the cell state. Also, excessively low erased V.sub.t will lower the cell punch-through voltage and impede subsequent programming of other cells on the same bitline (see discussion of FIG. 6 below).
Flash programming to a high V.sub.t prior to erase is a good idea, as in FIG. 4. It can also be accomplished using a grounded substrate and higher gate voltage. It is only useful for "flash" programming prior to erase because all cells obtain the same state. By necessity, this approach requires flash erase to a low V.sub.t with the associated problems (see discussion of FIG. 3 above).
The principle of FIG. 5 is the same as FIG. 3. However, a portion of the erase tunnelling current flows to the substrate. The same problems of erase V.sub.t distribution discussed in FIG. 3 occur for this condition. Also, temporary electron trapping in the channel region can cause inaccurate V.sub.t sensing during the erase verification cycles.
In FIG. 6, the standard CHE programming requires high current levels. Also, the punch-through (VDTO) of unaddressed cells on a bitline can pin the bitline voltage at a level that is too low to permit programming of the selected bit on that bitline. In practice, this limits the minimum channel length that can be used in the array. The proposed programming technique of the instant invention should be less susceptible to this since cells can be designed to program at drain voltages lower than V.sub.CC.
One feature of this proposed technique is that the speed of programming for an individual cell will be substantially longer than for CHE. However, since little current is required during programming, many cells can be programmed simultaneously. This means that on-board latches will be needed to hold the required data during programming. In practice, the programming time for a typical block of data will be about the same using our technique as for using CHE, and the extra area needed (overhead) for data latches should be negligible.
Some of the problems in designing and fabricating flash EEPROM cells include over-erasing cells where the cell threshold voltage V.sub.t becomes negative and, on the other end of the distribution curve, cells that have threshold voltages above the normal maximum allowed erase V.sub.t, in which case an erased cell will be read as a programmed cell.
An EEPROM cell is over-erased when an excess of electrons is removed from the floating gate during the erase operation creating a conducting path between the source and drain when the control gate and the source are at the same voltage. Over-erased cells create read cycle inaccuracies.
In a conventional EEPROM cell, as described in U.S. Pat. No. 5,122,985 issued on Jun. 16, 1992 to Santin, the floating gate of a properly programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen wordline select voltage, i.e., V.sub.CC, is applied to the control gate. This nonconductive state is read as a "zero" bit.
The floating gate of a non-programmed cell is positively charged, neutrally charged, or slightly negatively charged, such that the source-drain path under the non-programmed floating gate is conductive when the same chosen wordline select voltage V.sub.CC is applied to the control gate This conductive state is read as a "one" bit.
After conventional programming, the distribution of threshold voltage V.sub.t is shifted to a higher range, i.e., +4 to +9 volts; and, after erasing, the V.sub.t is lowered to a range of perhaps 1-3.5 volts.